Aix-Marseille Université

Post-doctoral position in « Contribution to the design and optimization of an ultra-low power microcontroller for medical devices »

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Driven by the proliferation of wireless and low-cost applications, it is expected that the Internet of Things (IoT) will occupy a predominant position in our societies where individuals as well as objects are more and more connected. However, this expansion is limited by the energy consumption of microelectronic circuits embedded in complex objects. For applications relying on energy harvesting, the energy efficiency is the key parameter to optimize. Indeed, as opposed to standard IoT devices, which offer variety of services by taking advantage of a macroscopic energy reserve offered by their battery, systems based on energy harvesting perform very specific operations with a reduced energy budget while consuming little or no power when switched to standby mode.

In this context, electronic chips with high integration density, ultra-low power consumption, low leakage currents, good immunity to radiation and operating with a supply voltage lower than 0.6 V, have been recently published. These chips rely on microcontrollers having an ARM M0[1] core synthesized in 28 nm FDSOI (Fully Depleted Silicon-On-Insulator) technology with a dynamic power consumption of 2.7 pJ per cycle have been recently presented. However, in deep sleep mode where fast clocks are paused, these microcontrollers, embedding volatile RAM memory, still have a power consumption of 0.7 µW. To use these types of microcontrollers in implantable medical devices such as those developed by CAIRDAC[2], power consumption must be further more reduced. Indeed, in an implantable medical device, the microcontroller is 99% of the time in deep sleep mode. Thus, techniques for reducing energy consumption must target this operating stage where most of the peripherals are off or put in a “degraded” operation mode.

Position description

The objective of the work will be the reduction by a factor of three, at least, of the deep sleep mode power consumption of the microcontrollers embedded in CAIRDAC medical devices, while preserving the integrity of the data stored in the volatile memory. In addition, during normal operation, the computational capacities of the microcontroller, required for controlling the clinical algorithms embedded in the implant, must be maintained. The microcontroller will be designed using a 28nm FDSOI technology from STMicroelectronics with the support of STMicroelectronics in the context of a European Nano2022 program. Prototyping will be based on the CMP (Multi ‐ Project Circuits) platform in Grenoble, which offers FDSOI 28 nm technology in its fabrication process catalog. To reduce consumption, several options will be explored:

  1. The first option is related to the use of the FDSOI technology itself, which provides high performances and energy efficient transistors while allowing high density. To mitigate current leakages, FDSOI technology uses a very thin layer of silicon (used as a substrate for transistors) placed on a layer of insulating silicon oxide. In addition, the operating regimes of the transistor can be optimized by applying a voltage to its back gate. Thus, depending on the voltages applied to the transistor gates, its properties can be modified to reduce energy consumption.
  2. The second option is related to the reduction of the power consumption in standby mode of the SRAM memory embedded in the microcontroller. This reduction will be achieved by decreasing the operating voltage of the SRAM memory to its minimum retention voltage. At this level, different SRAM cell architectures will be designed and evaluated within an elementary memory array (1kbytes) including sense amplifiers, pre-charge circuits, write drivers and control logic.
  3. The third option will address the optimization of the clock generation circuit of the microcontroller during all operating modes. At this level, the choice of the proper operating frequencies in standby, but also in normal operating modes will be a key parameter. Indeed, most of the microcontrollers operate at frequencies of several tens of MHz while the need for CAIRDAC is 1 MHz in nominal operation. This specification gives more latitude to optimize the architecture of the microcontroller.

The technical approach of this work will aim to demonstrate the feasibility of an energy efficient system adapted to a given energy harvester, while exclusively using the latest technologies in the manufacturing and design of electronic chips. A rigorous analysis of the architecture of a Cortex-M0 + processor core will be carried out in order to define operating modes where power consumption is relevant for medical devices. Beforehand, a license to use a Cortex-M0 + core will be requested from ARM (university license). Partitioning of the processor core will be necessary in order to implement original low-consumption techniques, but also to effectively integrate or modify some modules (clock generation circuits, SRAM memory and power management circuit).

Note that a post-doc will be backed up by the support of ST-Microelectronics as well as a PhD student fully dedicated to the topic.

Searched profile:

Ideally, the candidate should have a PhD in integrated circuit design and skills in one of the following points:

  • design and simulation flow of digital and/or analog integrated circuits;
  • microcontroller energy consumption optimization strategies;
  • FD-SOI 28 nm CMOS technology.

Starting date: January 2022

Duration: 12 months


H. AZIZA: hassen.aziza@univ-amu.fr

R. VAUCHE: remy.vauche@univ-amu.fr

Net Salary: from 1900€ to 2400€ according to the hired profile

Job Location: Laboratoire IM2NP Lab (https://www.im2np.fr), Technopôle de Château Gombert

05, Rue Enrico Fermi - Bât Fermi, Marseille, France 

[1] https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0

[2] http://www.cairdac.com

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Post-doctoral position in « Contribution to the design and optimization of an ultra-low power microcontroller for medical devices »
Jardin du Pharo 58, bd Charles Livon Marseille, France
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